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5-142 march 1997 hd-15530 cmos manchester encoder-decoder features ? support of mll-std-1553 ? data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 mbit/s ? sync identi?cation and lock-in ? clock recovery ? manchester ii encode, decode ? separate encode and decode ? low operating power . . . . . . . . . . . . . . . . . 50mw at 5v description the intersil hd-15530 is a high performance cmos device intended to service the requirements of mll-std-1553 and similar manchester ii encoded, time division multiplexed serial data protocols. this lsi chip is divided into two sections, an encoder and a decoder. these sections operate completely independent of each other, except for the master reset functions. this circuit meets many of the requirements of mil-std- 1553. the encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. the decoder recognizes the sync pulse and identi?es it as well as decod- ing the data bits and checking parity. this integrated circuit is fully guaranteed to support the 1mhz data rate of mll-std-1553 over both temperature and voltage. it interfaces with cmos, ttl or n channel support circuitry, and uses a standard 5v supply. the hd-15530 can also be used in many party line digital data communications applications, such as an environmen- tal control system driven from a single twisted pair cable of ?ber optic cable throughout the building. pinouts hd-15530 (cerdip, pdip) top view hd-15530 (clcc) top view ordering information package temp. range 1.25 megabit/s pkg. no. cerdip -40 o c to +85 o c HD1-15530-9 f24.6 -55 o c to +125 o c hd1-15530-8 smd# 7802901ja clcc -40 o c to +85 o c hd4-15530-9 j28.a -55 o c to +125 o c hd4-15530-8 smd# 78029013a pdip -40 o c to +85 o c hd3-15530-9 e24.6 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 valid word encoder take data serial data out decoder clk bipolar zero in bipolar one in unipolar data in decoder shift clk command/ decoder reset gnd v cc send clk in send data sync select encoder enable bipolar one out bipolar ? 6 out master reset encoder clk serial data in output inhibit d a t a sync shift clk zer o out 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 decoder nc nc bipolar bipolar unipolar decoder send nc nc sync encoder serial bipolar command/ decoder gnd master ? 6 out output bipolar serial take data encoder v cc encoder valid send clk zero in one in data in shift clk data out shift clk clk clk in word data select enable data in one out d a t a sync reset reset zer o out inhibit file number 2960.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
5-143 block diagrams encoder decoder gnd master reset send clk in ? 6 out bit counter character 12 13 22 14 ? 6 encoder clk 23 former ? 2 21 2 18 19 20 15 17 send data serial data in encoder enable sync select encoder 16 bipolar one out bipolar zer o out 24 output inhibit v cc shift clk 7 6 unipolar data in bipolar one in bipolar zero in decoder clk master reset 8 transition finder synchronizer 5 13 decoder reset 11 bit counter bit rate clk parity check 9 1 decoder shift clk character identifier 10 3 valid word serial data out command/ d a t a sync take data 4 pin description pin number type name section description 1 o valid word decoder output high indicates receipt of a valid word, (valid parity and no manches- ter errors). 2 o encoder shift clock encoder output for shifting data into the encoder. the encoder samples sdi on the low-to-high transition of encoder shift clock. 3 o take data decoder output is high during receipt of data after identi?cation of a sync pulse and two valid manchester data bits. 4 o serial data out decoder delivers received data in correct nrz format. 5 i decoder clock decoder input drives the transition ?nder, and the synchronizer which in turn supplies the clock to the balance of the decoder, input a frequency equal to 12x the data rate. 6 i bipolar zero in decoder a high input should be applied when the bus is in its negative state. this pin must be held high when the unipolar input is used. 7 i bipolar one in decoder a high input should be applied when the bus is in its positive state. this pin must be held low when the unipolar input is used. 8 i unlpolar data in decoder with pin 6 high and pin 7 low, this pin enters unipolar data into the transition ?nder circuit. if not used this input must be held low. 9 o decoder shift clock decoder output which delivers a frequency (decoder clock ? 12), synchro- nized by the recovered serial data stream. 10 o command sync decoder output of a high from this pin occurs during output of decoded data which was preceded by a command (or status) synchronizing character. a low output indicates a data synchronizing character. 11 i decoder reset decoder a high input to this pin during a rising edge of decoder shift clock resets the decoder bit counting logic to a condition ready for a new word. 12 i ground both ground supply pin. 13 i master reset both a high on this pin clears 2:1 counters in both encoder and decoder, and resets the ? 6 circuit. 14 o ? 6 out encoder output from 6:1 divider which is driven by the encoder clock. 15 o bipolar zer o out encoder an active low output designed to drive the zero or negative sense of a bipolar line driver. 16 i output inhibit encoder a low on this pin forces pin 15 and 17 high, the inactive states. 17 o bipolar one out encoder an active low output designed to drive the one or positive sense of a bipolar line driver. hd-15530
5-144 encoder operation the encoder requires a single clock with a frequency of twice the desired data rate applied at the send clock input. an auxiliary divide by six counter is provided on chip which can be utilized to produce the send clock by divid- ing the decoder clock. the encoders cycle begins when encoder enable is high during a falling edge of encoder shift clock . this cycle lasts for one word length or twenty encoder shift clock periods. at the next low-to-high transition of the encoder shift clock, a high sync select input actuates a command sync or a low will produce a data sync for the word . when the encoder is ready to accept data, the send data output will go high and remain high for six- teen encoder shift clock periods . during these sixteen periods the data should be clocked into the serial data input with every high-to-low transition of the encoder shift clock so it can be sampled on the low- to-high transition - . after the sync and manchester ii coded data are transmitted through the bipolar one and bipolar zer o outputs, the encoder adds on an additional bit which is the parity for that word . if encoder enable is held high continuously, consecutive words will be encoded without an interframe gap. encoder enable must go low by time as shown to prevent a consecutive word from being encoded. at any time a low on output inhibit input will force both bipolar outputs to a high state but will not affect the encoder in any other way. to abort the encoder transmission a positive pulse must be applied at master reset. anytime after or during this pulse, a low-to-high transition on send clock clears the internal counters and initializes the encoder for a new word. 18 i serial data in encoder accepts a serial data stream at a data rate equal to encoder shift clock. 19 i encoder enable encoder a high on this pin initiates the encode cycle. (subject to the preceeding cycle being complete.) 20 i sync select encoder actuates a command sync for an input high and data sync for an input low. 21 o send data encoder an active high output which enables the external source of serial data. 22 i send clock in encoder clock input at a frequency equal to the data rate x2, usually driven by ? 6 output. 23 i encoder clock encoder input to the 6:1 divider, a frequency equal to the data rate x12 is usually input here. 24 i v cc both v cc is the +5v power supply pin. a 0.1 m f decoupling capacitor from v cc (pin 24) to ground (pin 12) is recommended. i = input o = output pin description (continued) pin number type name section description 1 2 3 3 4 5 5 figure 1. dont care valid dont care p 0 1 2 3 p 0 1 2 3 0 1 2 3 19 15 16 17 18 7 6 5 4 11 12 13 14 15 11 12 13 14 15 11 12 13 14 15 10 sync sync 2nd half 1st half 3 2 1 0 timing send clk encoder shift clk encoder sync select send data serial bipolar one out bipolar zer o out 1 2 3 4 5 enable data in hd-15530
5-145 decoder operation the decoder requires a single clock with a frequency of 12 times the desired data rate applied at the decoder clock input. the manchester ii coded data can be presented to the decoder in one of two ways. the bipolar one and bipolar zero inputs will accept data from a comparator sensed transformer coupled bus as speci?ed in military spec 1553. the unipolar data input can only accept non-inverted manchester ii coded data. (e.g. from bipolar one out of an encoder through an inverter to unipolar data input). the decoder is free running and continuously monitors its data input lines for a valid sync character and two valid manchester data bits to start an output cycle. when a valid sync is recognized , the type of sync is indicated on command/ d a t a sync output. if the sync character was a command sync, this output will go high and remain high for sixteen decoder shift clock periods , otherwise it will remain low. the take data output will go high and remain high - while the decoder is transmitting the decoded data through serial data out. the decoded data available at serial data out is in nrz format. the decoder shift clock is provided so that the decoded bits can be shifted into an external register on every low-to- high transition of this clock - . note that decoder shift clock may adjust its phase up until the time that take data goes high. after all sixteen decoded bits have been transmitted the data is checked for odd parity. a high on valid word output indicates a successful reception of a word without any manchester or parity errors. at this time the decoder is looking for a new sync character to start another output sequence. valid word will go low approximately 20 decoder shift clock periods after it goes high if not reset low sooner by a valid sync and two valid manchester bits as shown . at any time in the above sequence a high input on decoder reset during a low-to-high transition of decoder shift clock will abort transmission and ini- tialize the decoder to start looking for a new sync character. 1 2 3 2 3 2 3 3 4 1 figure 2. undefined p 0 1 2 p 0 1 2 1 2 3 40 16 17 18 19 7 6 5 4 11 12 13 14 15 11 12 13 14 15 12 13 14 15 sync sync 2nd half 1st half 3 2 1 0 timing decoder shift clk command/ take data serial 8 10 10 1 2 3 4 data out bipolar one in bipolar zero in (from previous reception) valid word data sync hd-15530
5-146 how to make our mtu look like a manchester encoded uart typical timing diagrams for a manchester encoded uart figure 4. encoder timing figure 5. decoder timing figure 3. 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 valid word decoder bipolar bipolar unipolar command decoder v cc sync encoder bipolar bipolar master output sync encoder clk zer o out reset data in one in zero in select enable one out inhibit reset a b ck h 74ls164 ab ck 74ls164 parallel out o h sh/ld ck si 74165 ck 74165 parallel in sh/ld o h encoder enable sync select parallel in valid valid bipolar one out bipolar zero out sync msb lsb parity p p sync msb lsb parity p bipolar one in bipolar zero in command sync parallel out valid word from previous reception valid valid p hd-15530
5-147 mil-std-1553 the 1553 standard de?nes a time division multiplexed data bus for application within aircraft. the bus is de?ned to be bipolar, and encoded in a manchester ii format, so no dc component appears on the bus. this allows transformer coupling and excellent isolation among systems and their environment. the hd-15530 supports the full bipolar con?guration, assuming a bus driver con?guration similar to that in figure 1. bipolar inputs from the bus, like figure 2, are also accom- modated. the signaling format in mll-std-1553 is speci?ed on the assumption that the network of 32 or fewer terminals are controlled by a central control unit by means of command words. terminals respond with status words. each word is preceded by a synchronizing pulse, and followed by parity bit, occupying a total of 20 m s. the word formats are shown in figure 4. the special abbreviations are as follows: p parity, which is de?ned to be odd, taken across all 17 bits. r/t receive on logical zero, transmit on one. me message error if logical 1. tf terminal flat, if set, calls for controller to request self-test data. the paragraphs above are intended only to suggest the content of mll-std-1553, and do not completely describe its bus requirements, timing or protocols. figure 6. simplified mil-std-1553 driver figure 7. simplified mil-std-1553 receiver figure 8. mil-std-1553 character formats figure 9. mil-std-1553 word formats note: this page is a summary of mil-std-1553 and is not intended to describe the operation of the hd-15530. 1 0 bus 0 1 bus + - + - 1 ref 0 ref command sync sync data period bit period bit period bit logical one data logical zero data 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5551 p data word count sub address /mode terminal address sync command word (from controller to terminal) 1 r/t 16 1 p sync data word (sent either direction) 591 p code for failure modes terminal address sync status word (from terminal to controller) 1 me tf 1 control word hd-15530
5-148 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.3v to v cc +0.3v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v temperature range (t a ) hd-15530-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c hd-15530-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c encoder/decoder clock rise time . . . . . . . . . . . . . . . . . . .8ns max encoder/decoder clock fall time . . . . . . . . . . . . . . . . . . . .8ns max sync transition span (td2) . . . . . . . . . . . . . . . 18 tdc typ (note 1) short data transition span (td4) . . . . . . . . . . . 6 tdc typ (note 1) long data transition span (td5) . . . . . . . . . . . 12 tdc typ (note 1) thermal resistance (typical) q ja ( o c/w) q jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 55 12 clcc package . . . . . . . . . . . . . . . . . . 65 14 plastic dip package . . . . . . . . . . . . . . 60 n/a maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . .-65 o c to +150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not impli ed. dc electrical speci?cations v cc = 5v 10%, t a = -40 o c to +85 o c (hd-15530-9) t a = -55 o c to +125 o c (hd-15530-8) parameter symbol limits test conditions units min max input low voltage v il - 0.2 v cc v cc = 4.5v and 5.5v v input high voltage v lh 0.7 v cc -v cc = 4.5v and 5.5v v input low clock voltage v ilc - gnd +0.5 v cc = 4.5v and 5.5v v input high clock voltage v ihc v cc -0.5 - v cc = 4.5v and 5.5v v output low voltage v ol - 0.4 i ol = 1.8ma (note 2), v cc = 4.5v v output high voltage v oh 2.4 - i oh = -3ma (note 2), v cc = 4.5v v input leakage current i i -1.0 +1.0 v i = gnd or v cc , v cc = 5.5v m a standby supply current i ccsb -2v in = v cc = 5.5v output open ma operating power supply current i ccop -10v cc = 5.5v, v in = v cc , f =15mhz, outputs open ma function test f t - - (note 3) - notes: 1. tdc = decoder clock period = 1/fdc 2. interchanging of force and sense conditions is permitted. 3. tested as follows: = f = 15mhz, v ih = 70% v cc , v il = 20% v cc , c l = 50pf, v oh 3 1.5v and v ol 1.5v. capacitance t a = +25 o c; frequency = 1mhz symbol parameter typical units conditions c in input capacitance 15 pf all measurements are referenced to device gnd c o output capacitance 15 pf hd-15530
5-149 ac electrical speci?cations v cc = 5v 10%, t a = -40 o c to +85 o c (hd-15530-9) t a = -55 o c to +125 o c (hd-15530-8) parameter symbol (note 2) test conditions limits units min max encoder timing encoder clock frequency fec v cc = 4.5v and 5.5v, c l = 50pf - 15 mhz send clock frequency fesc v cc = 4.5v and 5.5v, c l = 50pf - 2.5 mhz encoder data rate fed v cc = 4.5v and 5.5v, c l = 50pf - 1.25 mhz master reset pulse width tmr v cc = 4.5v and 5.5v, c l = 50pf 150 - ns shift clock delay te1 v cc = 4.5v and 5.5v, c l = 50pf - 125 ns serial data setup te2 v cc = 4.5v and 5.5v, c l = 50pf 75 - ns serial data hold te3 v cc = 4.5v and 5.5v, c l = 50pf 75 - ns enable setup te4 v cc = 4.5v and 5.5v, c l = 50pf 90 - ns enable pulse width te5 v cc = 4.5v and 5.5v, c l = 50pf 100 - ns sync setup te6 v cc = 4.5v and 5.5v, c l = 50pf 55 - ns sync pulse width te7 v cc = 4.5v and 5.5v, c l = 50pf 150 - ns send data delay te8 v cc = 4.5v and 5.5v, c l = 50pf 0 50 ns bipolar output delay te9 v cc = 4.5v and 5.5v, c l = 50pf - 130 ns enable hold te10 v cc = 4.5v and 5.5v, c l = 50pf 10 - ns sync hold te11 v cc = 4.5v and 5.5v, c l = 50pf 95 - ns decoder timing decoder clock frequency fdc v cc = 4.5v and 5.5v, c l = 50pf - 15 mhz decoder data rate fdd v cc = 4.5v and 5.5v, c l = 50pf - 1.25 mhz decoder reset pulse width tdr v cc = 4.5v and 5.5v, c l = 50pf 150 - ns decoder reset setup time tdrs v cc = 4.5v and 5.5v, c l = 50pf 75 - ns decoder reset hold time tdrh v cc = 4.5v and 5.5v, c l = 50pf 10 - ns master reset pulse tmr v cc = 4.5v and 5.5v, c l = 50pf 150 - ns bipolar data pulse width td1 v cc = 4.5v and 5.5v, c l = 50pf tdc + 10 (note 1) -ns one zero overlap td3 v cc = 4.5v and 5.5v, c l = 50pf - tdc - 10 (note 1) ns sync delay (on) td6 v cc = 4.5v and 5.5v, c l = 50pf -20 110 ns take data delay (on) td7 v cc = 4.5v and 5.5v, c l = 50pf 0 110 ns serial data out delay td8 v cc = 4.5v and 5.5v, c l = 50pf - 80 ns sync delay (off) td9 v cc = 4.5v and 5.5v, c l = 50pf 0 110 ns take data delay (off) td10 v cc = 4.5v and 5.5v, c l = 50pf 0 110 ns valid word delay td11 v cc = 4.5v and 5.5v, c l = 50pf 0 110 ns notes: 1. tdc = decoder clock period = 1/fdc 2. ac testing as follows: input levels: v ih = 70% v cc , v il = 20% v cc ; input rise/fall times driven at 1ns/v; timing reference levels: 1.5v; output load: c l = 50pf. hd-15530
5-150 timing waveforms figure 10. encoder timing figure 11. decoder timing send clock encoder shift clock serial data in send clock encoder shift clock encoder enable sync select encoder shift clock send data send clock bipolar one out or bipolar zer o out t e9 t e8 t e7 valid t e6 t e5 t e4 t e1 t e3 t e2 valid valid t e1 decoder shift clock command/ d a t a sync take data decoder shift clock serial data out decoder shift clock command/ d a t a sync take data valid word decoder shift clock decoder reset t d6 t d7 t d8 t d9 t d10 t d11 t drs t dr t drh data bit hd-15530
5-151 test load circuit ac testing input, output waveform figure 12. decoder timing timing waveforms (continued) bipolar one in t d1 bipolar zero in bipolar one in bipolar zero in bipolar one in bipolar zero in unipolar in t d2 t d3 t d1 t d2 t d3 bit period bit period bit period command sync t d1 t d2 t d3 t d1 data sync t d2 t d3 t d1 t d3 t d3 t d1 t d1 t d1 t d3 t d3 t d3 t d4 t d5 t d5 t d4 one zero one t d2 command sync t d2 t d2 t d2 t d5 t d5 t d4 t d4 t d4 unipolar in unipolar in one zero one data sync one note: bipolar one in = 0; bipolar zero in = 1, for next diagrams. note: unipolar in = 0, for next diagrams. cl9 dut note: includes stray and jig capacitance. (note) input v ih v il 50% 50% v oh v ol output ac testing: all input signals must switch between v il and v ih . input rise and fall times are driven at 1ns per volt. hd-15530
5-152 burn-in circuits hd1-15530 cerdip hd4-15530 clcc notes: 1. v cc = 5.5v 0.5v 2. v ih = 4.5v 10% 3. v il = -0.2v +0.4v 4. r1 = 47k w 5% 5. r2 = 1.8k w 5% 6. f0 = 100khz 10% 7. c1 = 0.01 m f min. 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 r1 gnd v cc r1 a r1 gnd r1 r1 a a gnd f0 a a a a r1 r1 r1 r1 gnd v cc r1 gnd r1 v cc r1 gnd r1 f0 a gnd v cc gnd v cc c1 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 gnd v cc r2 r2 gnd v cc gnd r2 r2 f0 gnd r2 r2 v cc r2 gnd r2 gnd gnd c1 gnd gnd nc nc r2 gnd gnd gnd gnd nc nc f0 hd-15530
5-153 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: 155 x 195 x 19mils metallization: type: si-al thickness: 11k ? 2k ? glassivation: type: sio 2 thickness: 8ka 1k ? worst case current density: 1.8 x 10 5 a/cm 2 metallization mask layout hd-15530 encoder valid encoder clk send clk in send data sync select encoder enable command/data sync decoder shift clk unipolar data in bipolar one in ? 6 out master gnd word shift clk serial data in bipolar one out output inhibit bipolar zer o out reset decoder reset bipolar zero in decoder clk serial data out take data v cc hd-15530

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